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st24lc21b, st24lw21 st24fc21, st24fw21 1 kbit (x8) dual mode serial eeprom for vesa plug & play january 1999 1/21 ai01741 sda v cc st24xy21 vclk scl v ss wc figure 1. logic diagram 1 million erase/write cycles 40 years data retention 3.6v to 5.5v single supply voltage hardware write control (st24lw21 and st24fw21) ttl schmitt-trigger on vclk input 100k / 400k hz compatibility with the i 2 c bus bit transfer range two wire serial interface i 2 c bus compatible i 2 c page write (up to 8 bytes) i 2 c byte, random and sequential read modes self timed programming cycle automatic address incrementing enhanced esd/latch up performances error recovery mechanism (st24fc21 and st24fw21) vesa 2 compatible description the st24lc21b, st24lw21, st24fc21 and st24fw21 are 1k bit electrically erasable pro- grammable memory (eeprom), organized in 128x8 bits. in the text, products are referred as st24xy21, where "x" is either "l" for vesa 1 or "f" for vesa 2 compatible memories and where "y" indicates the write control pin connection: "c" means wc on pin 7 and "w" means wc on pin 3. sda serial data address input/output scl serial clock (i 2 c mode) v cc supply voltage v ss ground vclk clock transmit only mode wc write control table 1. signal names 8 1 so8 (m) 150mil width 8 1 psdip8 (b) 0.25mm frame note: wc signal is only available for st24lw21 and st24fw21 products.
sda v ss scl vclk nc nc v cc nc ai01742 st24lc21b 1 2 3 4 8 7 6 5 figure 2a. dip pin connections 1 ai01743 2 3 4 8 7 6 5 sda v ss scl vclk nc nc v cc nc st24lc21b figure 2b. so pin connections warning: nc = not connected. warning: nc = not connected. sda v ss scl vclk nc nc v cc du ai01744 st24fc21 1 2 3 4 8 7 6 5 figure 2c. dip pin connections 1 ai01745 2 3 4 8 7 6 5 sda v ss scl vclk nc nc v cc du st24fc21 figure 2d. so pin connections warning: nc = not connected. du = dont use, must be left open or connected to v cc or v ss . sda v ss scl vclk nc nc v cc wc ai01746 st24fw21 st24lw21 1 2 3 4 8 7 6 5 figure 2e. dip pin connections 1 ai01747 2 3 4 8 7 6 5 sda v ss scl vclk nc nc v cc wc st24fw21 st24lw21 figure 2f. so pin connections warning: nc = not connected. warning: nc = not connected. warning: nc = not connected. du = dont use, must be left open or connected to v cc or v ss . 2/21 st24lc21b, st24lw21, st24fc21, st24fw21
symbol parameter value unit t a ambient operating temperature C40 to 85 c t stg storage temperature C65 to 150 c t lead lead temperature, soldering (so8 package) (psdip8 package) 40 sec 10 sec 215 260 c v io input or output voltages C0.3 to 6.5 v v cc supply voltage C0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) (2) 4000 v electrostatic discharge voltage (machine model) (3) 500 v notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and oth er relevant quality documents. 2. mil-std-883c, 3015.7 (100pf, 1500 w ). 3. eiaj ic-121 (condition c) (200pf, 0 w ). table 2. absolute maximum ratings (1) device code chip enable r w bit b7 b6 b5 b4 b3 b2 b1 b0 device select 1 0 1 0 x x x r w note: the msb b7 is sent first. x = 0 or 1. table 3. device select code the st24xy21 can operate in two modes: trans- mit-only mode and i 2 c bidirectional mode. when powered, the device is in transmit-only mode with eeprom data clocked out from the rising edge of the signal applied on vclk. the device will switch to the i 2 c bidirectional mode upon the falling edge of the signal applied on scl pin. when in i 2 c mode, the st24lc21b (or the st24lw21) cannot switch back to the transmit only mode (except when the power supply is re- moved). for the st24fc21 (or the st24fw21), after the falling edge of scl, the memory enter in a transition state which allowed to switch back to the transmit-only mode if no valid i 2 c activity is observed. the device operates with a power supply value as low as +3.6v. both plastic dual-in-line and plastic small outline packages are available. transmit only mode after a power-up, the st24xy21 is in the transmit only mode. a proper initialization sequence (see figure 3) must supply nine clock pulses on the vclk pin (in order to internally synchronize the device). during this initialization sequence, the sda pin is in high impedance. on the rising edge of the tenth pulse applied on vclk pin, the device will output the first bit of byte located at address 00h (most significant bit first). a byte is clocked out (on sda pin) with nine clock pulses on vclk: 8 clock pulses for the data byte and one extra clock pulse for a dont care bit. as long as the scl pin is held high, each byte of the memory array is transmitted serially on the sda pin with an automatic address increment. when the last byte is transmitted, the address counter will roll-over to location 00h. description (contd) 3/21 st24lc21b, st24lw21, st24fc21, st24fw21
ai01501 bit 7 v cc tvpu scl sda vclk bit 6 bit 7 v cc scl sda vclk bit 6 bit 6 bit 4 bit 0 1 2 8 9 10 11 12 13 17 18 19 20 bit 5 figure 3. transmit only mode waveforms mode r w bit st24lc21b st24fc21 vclk st24lw21 st24fw21 wc bytes initial sequence current address read 1 x x 1 start, device select, r w = 1 random address read 0 x x 1 start, device select, r w = 0, address, 1 x x restart, device select, r w = 1 sequential read 1 x x 1 to 128 similar to current or random mode byte write 0 v ih v ih 1 start, device select, r w = 0 page write 0 v ih v ih 8 start, device select, r w = 0 note: x = v ih or v il table 4. i 2 c operating modes 4/21 st24lc21b, st24lw21, st24fc21, st24fw21
i 2 c bidirectional mode the st24xy21 can be switched from transmit only mode to i 2 c bidirectional mode by applying a valid high to low transition on the scl pin (see figure 4). C when the st24lc21b (or the st24fc21) is in the i 2 c bidirectional mode, the vclk input (pin 7) enables (or inhibits) the execution of any write instruction: if vclk = 1, write instruc- tions are executed; if vclk = 0, write instruc- tions are not executed. C when the st24lw21 (or the st24fw21) is in the i 2 c bidirectional mode, the write control (wc on pin 3) input enables (or inhibits) the execution of any write instruction: if wc = 1, write instructions are executed;if wc = 0, write instructions are not executed. the st24xy21 is compatible with the i 2 c standard, two wire serial interface which uses a bidirectional data bus and serial clock. the device carries a built-in 4 bit, unique device identification code (1010) named device select code corresponding to the i 2 c bus definition. the st24xy21 behaves as a slave device in the i 2 c protocol with all memory operations synchro- nized by the serial clock scl. read and write operations are initiated by a start condition gen- erated by the bus master. the start condition is followed by a stream of 7 bits (device select code 1010xxx), plus one read/write bit and terminated by an acknowledge bit. when data is written into the memory, the st24xy21 responds to the 8 bits received by as- serting an acknowledge bit during the 9th bit time. when data is read by the bus master, it must acknowledges the receipt of the data bytes in the same way. data transfers are terminated with a stop condition (see read and write descrip- tions in the following pages). power on reset: v cc lock out write protect in order to prevent data corruption and inadvertent write operations during power up, a power on reset (por) circuit is implemented. until the v cc voltage has reached the por threshold value (around 3v), the internal reset is active, all opera- tions are disabled and the device will not respond to any command. in the same way, when v cc drops down from the operating voltage to below the por threshold value, all operations are disabled and the device will not respond to any command. a stable v cc must be applied before applying any logic signal. ai01892 scl sda vclk transmit only mode 1 2 89 msb ack start condition - temporary bi-directional mode (st24fc21 and st24fw21) - locked bi-directional mode (st24lc21b and st24lw21) - locked bi-directional mode (st24fc21 and st24fw21) figure 4. transition from transmit only (ddc1) to bi-directional (ddc2b) mode waveforms 5/21 st24lc21b, st24lw21, st24fc21, st24fw21
ai01748 switch back to transmit-only mode memory power on internal address pointer = 0 vclk yes no no send data bit (msb first) pointed by the address pointer and auto-increment pointed bit/byte scl yes no sda hi-z vclk internal counter = 0 start internal 2 sec timer scl yes reset vclk internal counter and reset internal timer valid i 2 c access (start + device select) ? yes vclk yes increment vclk counter counter = 128 or timer > 2 sec yes i 2 c communication idle waiting for a device select byte reset counter and timer send acknowledge respond to the incoming i 2 c command transition state (vesa 2) transmit-only mode (ddc1) i 2 c mode (ddc2b) no no figure 5. error recovery mechanism flowchart for the st24fc21 and st24fw21 products 6/21 st24lc21b, st24lw21, st24fc21, st24fw21
ai01665 v cc c bus sda r l master r l scl c bus 100 0 4 8 12 16 20 c bus (pf) maximum rp value (k w ) 10 1000 fc = 400khz fc = 100khz figure 6. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus error recovery modes available in the st24fc21 and the st24fw21 when the st24fc21 (or the st24fw21) first switches to the i 2 c mode (vesa ddc2b mode), it enters a transition state which is functionally iden- tical to i 2 c operation. but, if the st24fc21 (or the st24fw21) does not received a valid i 2 c se- quence, that is a start condition followed by a valid device select code (1010xxx r w), within either 128 vclk periods or a period of time of t recovery (approximately 2 seconds), the st24fc21 (or the st24fw21) will revert to the transmit-only mode (vesa ddc1 mode). if the st24fc21 (or the st24fw21) decodes a valid i 2 c device select code, it will lock into i 2 c mode. under this condition, signals applied on the vclk input will not disturb read access from the st24fc21 (or the st24fw21). for write ac- cess, refer to the signal description paragraph. when in the transition state, the count of vclk pulses and the internal 2 seconds timer are reset by any activity on the scl line. this means that, after each high to low transition on scl, the mem- ory will re-initialise its transition state and will switch back to transmit-only mode only after 128 more vclk pulses or after a new t recovery delay. signal descriptions i 2 c serial clock (scl). the scl input pin is used to synchronize all data in and out of the memory. a resistor can be connected from the scl line to v cc to act as a pull up (see figure 6). serial data (sda). the sda pin is bi-directional and is used to transfer data in or out of the memory. it is an open drain output that may be wire-ored with other open drain or open collector signals on the bus. a resistor must be connected from the sda bus line to v cc to act as pull up (see figure 6). transmit only clock (vclk) . the vclk input pin is used to synchronize data out when the st24xy21 is in transmit only mode. for the st24lc21b and the st24fc21 only, the vclk offers also a write enable (active high) func- tion when the st24lc21b and the st24fc21 are in i 2 c bidirectional mode. write control (wc). an hardware write control feature (wc) is offered only on st24lw21 and st24fw21 on pin 3. this feature is usefull to protect the contents of the memory from any erro- neous erase/write cycle. the write control signal is used to enable (wc = v il ) or disable (wc = v ih ) the internal write protection. when unconnected, the wc input is internally tied to v ss by a 100k ohm pull-down resistor and the memory is write pro- tected. 7/21 st24lc21b, st24lw21, st24fc21, st24fw21
symbol parameter test condition min max unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf t lp low-pass filter input time constant (sda and scl) 200 500 ns note: 1. sampled only, not 100% tested. table 5. input parameters (1) (t a = 25 c, f = 100 khz ) symbol parameter test condition min max unit i li input leakage current 0v v in v cc 2 m a i lo output leakage current 0v v out v cc sda in hi-z 2 m a i cc supply current v cc = 5v, f c = 400khz (rise/fall time < 10ns) 2ma supply current v cc = 3.6v, f c = 400khz 1 ma i cc1 supply current (standby) v in = v ss or v cc , v cc = 5v, f c = 0 100 m a v in = v ss or v cc , v cc = 5v, f c = 400khz 300 m a i cc2 supply current (standby) v in = v ss or v cc , v cc = 3.6v, f c = 0 30 m a v in = v ss or v cc , v cc = 3.6v, f c = 400khz 100 m a v il input low voltage (scl, sda, wc) C0.3 0.3 v cc v v ih input high voltage (scl, sda, wc) 0.7 v cc v cc + 1 v v p high level threshold voltage (schmitt trigger on vlck) v cc = 5.5v 1.4 2.1 v v cc = 4.5v 1.2 1.9 v v cc = 3.6v 1 1.7 v v n low level threshold voltage (schmitt trigger on vlck) v cc = 5.5v 0.6 1.4 v v cc = 4.5v 0.5 1.2 v v cc = 3.6v 0.4 1 v v h hysteresis voltage (schmitt trigger on vlck) v cc = 5.5v 0.4 1.5 v v cc = 4.5v 0.4 1.4 v v cc = 3.6v 0.35 1.3 v v ol output low voltage i ol = 3ma, v cc = 3.6v 0.4 v i ol = 6ma, v cc = 5v 0.6 v table 6. dc characteristics (t a = C40 to 85 c; v cc = 3.6v to 5.5v) 8/21 st24lc21b, st24lw21, st24fc21, st24fw21
symbol alt parameter min max unit t ch1ch2 (1) t r clock rise time 300 ns t cl1cl2 (1) t f clock fall time 300 ns t dh1dh2 (1) t r sda rise time 20 300 ns t dl1dl2 (1) t f sda fall time 20 300 ns t chdx (2) t su:sta clock high to input transition 600 ns t chcl t high clock pulse width high 600 ns t dlcl t hd:sta input low to clock low (start) 600 ns t cldx t hd:dat clock low to input transition 0 m s t clch t low clock pulse width low 1.3 m s t dxcx t su:dat input transition to clock transition 100 ns t chdh t su:sto clock high to input high (stop) 600 ns t dhdl t buf input high to input low (bus free) 1.3 m s t clqv t aa clock low to data out valid 200 900 ns t clqx t dh clock low to data out transition 200 ns f c f scl clock frequency 400 khz t w t wr write time 10 ms notes: 1. sampled only, not 100% tested. 2. for a restart condition, or following a write cycle. table 7. ac characteristics, i 2 c bidirectional mode for clock frequency = 400khz (t a = C40 to 85 c; v cc = 3.6v to 5.5v) device operation i 2 c bus background the st24xy21 supports the i 2 c protocol. this pro- tocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master will always initiate a data transfer and will provide the serial clock for syn- chronisation. the st24xy21 are always slave de- vices in all communications. start condition. start is identified by a high to low transition of the sda line while the clock scl is stable in the high state. a start condition must precede any command for data transfer. except during a programming cycle, the st24xy21 con- tinuously monitor the sda and scl signals for a start condition and will not respond unless one is given. stop condition. stop is identified by a low to high transition of the sda line while the clock scl is stable in the high state. a stop condition termi- nates communication between the st24xy21 and the bus master. a stop condition at the end of a read command (after the no ack) forces the standby state. a stop condition at the end of a write command triggers the internal eeprom write cycle. acknowledge bit (ack). an acknowledge signal is used to indicate a successfull data transfer. the bus transmitter, either master or slave, will release the sda bus after sending 8 bits of data. during the 9th clock pulse period the receiver pulls the sda bus low to acknowledge the receipt of the 8 bits of data. data input. during data input, the st24xy21 sam- ple the sda bus signal on the rising edge of the clock scl. note that for correct device operation the sda signal must be stable during the clock low to high transition and the data must change only when the scl line is low. 9/21 st24lc21b, st24lw21, st24fc21, st24fw21
symbol alt parameter min max unit t ch1ch2 t r clock rise time 1 m s t cl1cl2 t f clock fall time 300 ns t dh1dh2 t r input rise time 1 m s t dl1dl1 t f input fall time 300 ns t chdx (1) t su:sta clock high to input transition 4.7 m s t chcl t high clock pulse width high 4 m s t dlcl t hd:sta input low to clock low (start) 4 m s t cldx t hd:dat clock low to input transition 0 m s t clch t low clock pulse width low 4.7 m s t dxcx t su:dat input transition to clock transition 250 ns t chdh t su:sto clock high to input high (stop) 4.7 m s t dhdl t buf input high to input low (bus free) 4.7 m s t clqv (2) t aa clock low to next data out valid 0.2 3.5 m s t clqx t dh data out hold time 200 ns f c f scl clock frequency 100 khz t w t wr write time 10 ms notes: 1. for a restart condition, or following a write cycle. 2. the minimum value delays the falling/rising edge of sda away from scl = 1 in order to avoid unwanted start and/or stop conditions. table 8. ac characteristics, i 2 c bidirectional mode for clock frequency = 100khz (t a = C40 to 85 c; v cc = 3.6v to 5.5v) symbol alt parameter min max unit t vchqx t vaa output valid from vclk 500 ns t vchvcl t vhigh vclk high time 600 ns t vclvch t vlow vclk low time 1.3 m s t clqz t vhz mode tansition time 500 ns t vpu (1,2) transmit-only power-up time 0 ns t vh1vh2 (2) t r vclk rise time 1 m s t vl1vl2 (2) t f vclk fall time 1 m s t recovery (2) recovery time 1.5 3.5 sec notes: 1. refer to figure 3. 2. sampled only, not 100% tested. table 9. ac characteristics, transmit-only mode (t a = C40 to 85 c; v cc = 3.6v to 5.5v) 10/21 st24lc21b, st24lw21, st24fc21, st24fw21
scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop & bus free data valid tclqv tclqx data output tdhdl tchdh stop condition tchdx start condition write cycle tw ai01503 vclk sda tvchqx tclqz scl tvchvcl tvclvch figure 7. ac waveforms 11/21 st24lc21b, st24lw21, st24fc21, st24fw21
ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc figure 8. ac testing input output waveforms scl sda scl sda sda start condition sda input sda change ai00792 stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition figure 9. i 2 c bus protocol input rise and fall times 50ns input pulse voltages sda, scl 0.2v cc to 0.8v cc input pulse voltages v clk 0.4v to 2.4v input and output timing ref. voltages 0.3v cc to 0.7v cc table 10. ac measurement conditions 12/21 st24lc21b, st24lw21, st24fc21, st24fw21
memory addressing. to start communication be- tween the bus master and the slave st24xy21, the master must initiate a start condition. following this, the master sends onto the sda bus line 8 bits (msb first) corresponding to the device select code (7 bits) and a read or write bit. the 4 most significant bits of the device select code are the device type identifier, corresponding to the i 2 c bus definition. for these memories the 4 bits are fixed as 1010b. the following 3 bits are dont care. the 8th bit sent is the read or write bit (r w), this bit is set to 1 for read and 0 for write operations. if a match is found, the corresponding memory will acknowledge the identification on the sda bus during the 9th bit time. write operations following a start condition the master sends a device select code with the r w bit set to 0. the memory acknowledges this and waits for a byte address. after receipt of the byte address the de- vice again responds with an acknowledge. in i 2 c bidirectional mode, any write command with vclk=0 (for the st24lc21b and st24fc21) or with wc=0 (for the st24lw21 and st24fw21) will not modify data and will be acknowledged on data bytes, as shown in figure 12. byte write . in the byte write mode the master sends one data byte, which is acknowledged by the memory. the master then terminates the transfer by generating a stop condition. write cycle in progress ai01099b next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop proceed write operation proceed random address read operation send byte address first byte of instruction with rw = 0 already decoded by st24xxx figure 10. write cycle polling using ack 13/21 st24lc21b, st24lw21, st24fc21, st24fw21
page write. the page write mode allows up to 8 bytes to be written in a single write cycle, provided that they are all located in the same row in the memory: that is the most significant memory ad- dress bits are the same. the master sends from one up to 8 bytes of data, which are each acknow- ledged by the memory. after each byte is transfered, the internal byte address counter (3 least significant bits only) is incremented. the transfer is terminated by the master generating a stop condition. care must be taken to avoid address counter roll-over which could result in data being overwritten. note that, for any write mode, the generation by the master of the stop condition starts the internal memory pro- gram cycle. all inputs are disabled until the comple- tion of this cycle and the memory will not respond to any request. minimizing system delays by polling on ack . during the internal write cycle, the memory discon- nects itself from the bus in order to copy the data from the internal latches to the memory cells. the maximum value of the write time (t w ) is given in the ac characteristics table, since the typical time is shorter, the time seen by the system may be re- duced by an ack polling sequence issued by the master. the sequence is as follows: C initial condition: a write is in progress (see fig- ure 10). C step 1: the master issues a start condition followed by a device select byte (1st byte of the new instruction). stop start byte write dev sel byte addr data in start page write dev sel byte addr data in 1 data in 2 ai01893 stop data in n ack ack ack r/w ack ack ack r/w ack ack vclk/wc vclk/wc figure 11. write modes sequence 14/21 st24lc21b, st24lw21, st24fc21, st24fw21
stop start byte write control byte word addr data start page write word add n data n data n + 1 ai01894 ack ack ack ack ack ack vclk/wc control byte data n + 7 stop ack ack figure 12. inhibited write when vclk/wc = 0 C step 2: if the memory is busy with the internal write cycle, no ack will be returned and the master goes back to step 1. if the memory has terminated the internal write cycle, it will respond with an ack, indicating that the mem- ory is ready to receive the second part of the instruction (the first byte of this instruction was already sent during step 1). read operations on delivery, the memory content is set at all "1s" (or ffh). current address read. the memory has an inter- nal byte address counter. each time a byte is read, this counter is incremented. for the current ad- dress read mode, following a start condition, the master sends the device select code with the r w bit set to 1. the memory acknowledges this and outputs the data byte addressed by the internal byte address counter. this counter is then incre- mented. the master must not acknowledge the data byte output and terminates the transfer with a stop condition. random address read. a dummy write is per- formed to load the address into the address counter, see figure 14. this is followed by a re- start condition send by the master and the de- vice select code is repeated with the rw bit set to 1. the memory acknowledges this and outputs the addressed data byte. the master must not ac- knowledge the data byte output and terminates the transfer with a stop condition. sequential read. this mode can be initiated with either a current address read or a random ad- dress read. however, in this case the master does acknowledge the data byte output and the memory continues to output the next byte in se- quence. to terminate the stream of bytes, the master must not acknowledge the last data byte output, and must generate a stop condition. the output data is from consecutive byte ad- dresses, with the internal byte address counter automatically incremented after each byte output. after a count of the last memory address, the address counter will roll-over and the memory will continue to output data. acknowledge in read mode. in all read modes the st24xy21 wait for an acknowledge during the 9th bit time. if the master does not pull the sda line low during this time, the st24xy21 terminate the data transfer and switches to a standby state. 15/21 st24lc21b, st24lw21, st24fc21, st24fw21
ai01749 vsync 100nf 47k w +5v scl sda +5v monitor vclk scl sda v ss v cc monitor host vga cable 14 15 12 9 figure 13. recommended schematic for vesa 2.0 specification note concerning the power supply voltage in the vesa 2.0 specification according to the vesa 2.0 specification, the st24xy21 can be supplied by either the monitor or by the host (using +5v on the vga cable pin 9) power supply. the easyest way to implement this is to use 2 diodes as described in the following schematic. the st24xy21 supply voltage will be decreased by 0.6v, which is the diode forward voltage drop, and will be below 4.5v. nevertheless, the st24xy21 remains operational and no input will be damaged if the applied voltage on any input complies with the absolute maximum ratings val- ues. under this condition, the threshold voltage of the schmitt-trigger (pin 7) will be decreased (as in table 6). refer to the an627 application note for more de- tailed information regarding the use and the protec- tion of the st24xy21 in a monitor application. 16/21 st24lc21b, st24lw21, st24fc21, st24fw21
start dev sel * byte addr start dev sel data out 1 ai00794c data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack figure 14. read modes sequence note: * the 7 most significant bits of dev sel bytes of a random read (1st byte and 3rd byte) must be identical. 17/21 st24lc21b, st24lw21, st24fc21, st24fw21
family range st24lc21b vesa 1 wc on pin 7 st24lw21 vesa 1 wc on pin 3 st24fc21 vesa 2 wc on pin 7 st24fw21 vesa 2 wc on pin 3 package b psdip8 0.25mm frame m so8 150mil width temperature range 1 0 to 70 c 6 C40 to 85 c option tr tape & reel packing example: st24lc21b m 1 tr ordering information scheme devices are shipped from the factory with the memory content set at all "1s" (ffh). for a list of available options (package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. 18/21 st24lc21b, st24lw21, st24fc21, st24fw21
psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b symb mm inches typ min max typ min max a 3.90 5.90 0.154 0.232 a1 0.49 C 0.019 C a2 3.30 5.30 0.130 0.209 b 0.36 0.56 0.014 0.022 b1 1.15 1.65 0.045 0.065 c 0.20 0.36 0.008 0.014 d 9.20 9.90 0.362 0.390 e 7.62 C C 0.300 C C e1 6.00 6.70 0.236 0.264 e1 2.54 C C 0.100 C C ea 7.80 C 0.307 C eb 10.00 0.394 l 3.00 3.80 0.118 0.150 n8 8 psdip8 drawing is not to scale. psdip8 - 8 pin plastic skinny dip, 0.25mm lead frame 19/21 st24lc21b, st24lw21, st24fc21, st24fw21
so-a e n cp b e a d c l a1 a 1 h h x 45? symb mm inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e1.27C C0.050C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004 so8 drawing is not to scale. so8 - 8 lead plastic small outline, 150 mils body width 20/21 st24lc21b, st24lw21, st24fc21, st24fw21
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved all other names are the property of their respective owners purchase of i 2 c components by stmicroelectronics, conveys a license under the ph ilips i 2 c patent. rights to use these components in an i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 21/21 st24lc21b, st24lw21, st24fc21, st24fw21

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